The present invention relates to a phase-locked loop.
In a phase-locked loop (hereafter sometimes abbreviated as PLL), the phase of an input pulse signal is compared with that of the output pulse of a voltage controlled oscillator circuit (hereafter sometimes referred to as VCO) by a phase comparator circuit. The output current of the phase comparator circuit representing the detected phase difference is supplied to a loop filter. The voltage generated by the loop filter is supplied to the above described voltage controlled oscillator to effect feedback control. The output pulse is thus synchronized to the input pulse. The loop filter functions to define the response characteristics and eliminate noises.
Since the oscillator circuit constituting the PLL is synchronized in phase to the input signal of the PLL, the transmitted frequency/phase modulated signal can be reproduced at the receiving side. Accordingly, it is possible to know at the receiving side what kind of frequency/phase modulation has been effected at the transmission side. As a result, the PLL can be used as a frequency/phase demodulator.
Further, the PLL can be used for tracking signals having the Doppler effect because it has a tracking property owing to the feedback. In addition, the PLL has narrow-band selectivity which sharply suppresses signals and noises other than the synchronized input signal. In recent years, therefore, the PLL is used also for timing signal extraction in PCM communication equipment employed in optical communication, for example. The PLL is widely used in fields other than the above described field.
It is desirable that the output signal of the PLL does not contain a frequency ripple. This frequency ripple is incurred when a ripple component is included in the output signal level of the phase comparator.
In the PLL of the prior art, the frequency ripple is reduced by a smoothing filter which is formed by adding a parallel capacitor to a resistor constituting the loop filter.
An example of such a phase synchronization circuit is disclosed in a literature entitled "Transmission Design Criteria for Synchronous Token Ring" by Keller, IEEE Journal on Selected in Communications, SAC-1 (1983).
The above described method is simple because the frequency ripple can be reduced by only adding a capacitor to the loop filter. If it is attempted to enhance the effect of reducing the frequency ripple, however, peaking is caused in the loop characteristic and the jitter component of the input signal is amplified. Therefore, it is difficult to reduce the frequency ripple while restraining the jitter.
That is to say, it is desirable to choose the time constant of the loop filter on the basis of the condition demanded for individual application of the phase-locked loop such as an especially short frequency acquisition time or small frequency ripples. However, this selected value is not a value desired from the viewpoint of jitter prevention or response improvement. As a result, satisfactory characteristics cannot be obtained.
It is possible to remove the ripple contained in the output of the phase comparator circuit by increasing the time constant of a capacitor and a resistor constituting the loop filter without using the above described parallel capacitor. However, this increased time constant degrades the response performance.
Further, the oscillator circuit of the PLL disclosed in the above described literature is configured to generate a pulse signal having a duty ratio of 50%. By utilizing the fact that the duty ratio of the oscillation signal is 50%, the phase comparator circuit detects the phase difference between the input signal and the oscillation signal (i.e., the output signal) and generates pulses having phase difference information thus detected. Accordingly, the precision in detection of phase difference is influenced by the duty ratio. In the phase comparator circuit of the above described literature, mutual interference is caused between detected two phase difference signals (T.sub.D, T.sub.U) representing the phase difference. In the above described literature, however, the mutual interference is not considered. Therefore, the detected phase difference is affected by this mutual interference between signals. Because of the above described problems, it is difficult to raise the operation speed of the phase comparator circuit of the prior art. Therefore, when the phase comparator circuit of the prior art is used in fields demanding high speed operation, such as optical communication, it is not necessarily sufficient.
In optical communication, a plurality of optical transmission modules respectively including PLL's are employed to produce timing signals on the basis of digital PCM-coded optical signals. The signal which has been transmitted through the optical cable arrives at the receiving side with high speed and jitter.
Upon input of the signal, the phase-locked loop used for such application must respond to the input signal at an increased speed to quickly acquire or pull in the input signal. After the input signal acquisition, the bandwidth of the PLL (or the bandwidth of the noise) must be kept small to suppress the input jitter. In general, however, the acquisition characteristics of the PLL contradict its jitter suppression characteristics. That is to say, reducing the time constant of the loop filter for fast acquisition expands the PLL bandwidth and deteriorates the jitter suppression characteristics.
A PLL circuit of the prior art capable of coping with this problem is described in the Japanese Post-Exam publication JP-B-59-12049 by Nagano et al (laid-open on Nov. 7, 1977 as Laid-Open No. 52-132760). In this PLL circuit, two time constant circuits are provided and changed over so as to shorten the time constant of the filter when the frequency difference between the input signal and the output signal of the voltage controlled oscillator has exceeded a predetermined value. In a PLL circuit described in the Japanese Laid-Open application No. JP-A-59-202736 by Chiba et al, laid open on Nov. 16, 1984, a detector for detecting whether the PLL is synchronized or not is disposed at the output side of the phase comparator, and the time constant of the loop filter is made small in the asynchronous state.
In the aforementioned PLL described in the above-mentioned JP-B-59-12049, the time constant of the loop filter is not changed over until the frequency of the input signal largely differs from the free running frequency (i.e., the oscillation frequency obtained when the input control voltage is zero) of the VCO. In the PLL described in the above-mentioned JP-A-59-202736, the time constant of the loop filter is changed over when the oscillation frequency of the VCO is not in synchronism with the input signal. Either of these PLL's shortens the acquisition time or pull-in time in the pull-out state. The acquisition or pull-in process of the PLL includes a process starting from the time when the PLL has been synchronized to the input signal and ending when the phase difference between the input signal and the VCO output signal reduces below a predetermined value. The time necessary for this process is also desired to be short. However, the above described two prior arts have problems as described below. In the acquisition process of the former mentioned prior art after the frequency difference between the input and the output of the VCO has decreased below a predetermined value, the acquisition time cannot be made sufficiently small because the narrow loop bandwidth suitable to jitter suppression is selected. In the acquisition process of the latter mentioned prior art after the PLL has been synchronized to the input signal, the acquisition time cannot be made sufficiently small because the narrow bandwidth suitable to jitter suppression is also selected.